1. Field of the Invention
The present invention relates to a bridge device that connects a plurality of buses included in a computer system.
2. Description of the Prior Art
In recent years, many computer systems have been developed where a single or several processor(s) is/are made to access as large a number of peripherals as possible to improve both the function and performance of the system. A plurality of local buses are installed in such a computer system, with a plurality of peripherals being connected to the local buses. In such topology, the peripherals are provided away from the processor with the local buses acting as the main routes. When reading and writing data, the processor transfers to and from the peripherals on buses and between buses. As a result, when the processor reads or writes data, the functioning and the performance of the computer system are affected by the data transfer rate on buses and between buses. often used in a computer system in which the above-mentioned topology is adopted. The PCI bus is explained in detail in PCI Local bus Specification, Rev. 2.1.
PCI buses are characterized by performing address transfer and data transfer using 32 signal lines according to time division multiplexing. Stream type data that is stored in consecutive addresses in the memory of a peripheral is transferred with high speed to another peripheral by multiplexing data transfer. The real value of such high speed transfer can be felt when transferring a large amount of data, for instance, an MPEG (Motion Picture Expert Group) video stream that occupies several dozen megabytes on a hard disk.
The methods by which devices (hereinafter a processor or a peripheral will be called a "device") in the computer system use the local buses is explained below. When transferring data via a local bus, a device needs to acquire the use of the local bus. A dedicated device called a arbitration unit that is installed for each PCI bus gives the use of the local bus to one of the devices in a PCI bus type computer system. The use of a local bus is explained below.
1. The acquirement of the Use of a Local Bus
The use of a local bus is given to one device after the device transfers a request signal that requests the use of the local bus (hereinafter abbreviated as an "REQ signal") to the arbitration unit and receives a grant signal that is output from the arbitration unit (hereinafter abbreviated as a "GNT signal").
After acquiring the use of the local bus as described above, the device transfers the address first when the local bus is idle, and then transfers data after asserting both the master data transfer ready signal (hereinafter called as the "IRDY (Initiator Ready) signal") and the target data transfer ready signal (hereinafter called as the "TRDY (Target Ready) signal").
2. Burst Data Transfer
An address and data are multiplexed via a local bus, so that an address and data are transferred in sequence. Such a kind of transfer is called "burst data transfer", and the number of pieces of data that are transferred in one "burst data transfer" is called the "burst data transfer length".
3. Lapse of a Use
The use acquired by one device lapses when a "STOP signal" is output the target device to which data is to be transferred. The "STOP signal" represents the stop of data transfer, and is output when the target device has not finished preparing for data transfer or when ongoing data transfer cannot be continued.
A timeout of the latency timer in the device that requests the use also causes the use of a local bus to lapse. The latency timer is a timer that sets the maximum period of time for which the requesting device can occupy the bus. The latency timer starts a countdown from a predetermined initial value just after the use of the bus commences, so that when the numerical value becomes "0", the use of the master device lapses if the GNT signal to the requesting device itself has been deasserted.
4. The Re-Acquirement of the Use of a Local Bus
When the use of a local bus lapses without data transfer having been completed, the requesting device stops the data transfer, releases the local bus, and retries the data transfer process starting from the acquirement of the use of the local bus. The interruption of data transfer by a STOP signal is called a "retry termination", and the continuation of data transfer after the "retry termination" is called a "retry operation".
In general, when data is transferred using a single local bus, the use of the local bus is acquired in the process that has been described. It should be noted here that the maximum number of devices that may be connected to one local bus is about five, considering the electrical load and stability. When a computer system needs to include more than the maximum number of devices, a plurality of local buses need to be installed in the computer system, with bridge devices being installed between the local buses. The devices in the computer system read and write data via the bridge devices.
Data transfer via a bridge device that is installed between two local buses in such a extended computer system is explained below.
1. Data Read via a Bridge Device
When a first device connected to a first local bus requests to read data from a second device connected to a second local bus, the bridge device acquires the use of the second local bus, and requests to read data from the second device connected to the second local bus in place of the first device, and cancels the use of the first local bus by the first device. Until the first device (hereinafter called the "master device") acquires the use of the first local bus again, data is sequentially read from the second device (hereinafter called the "target device"). The bridge device stores the data read from the target device in its internal buffer. When the master device acquires the use of the first local bus again, the bridge device sequentially outputs the data stored in the internal buffer to the master device. Such data read via a bridge device is called "delayed read".
2. Data Write via a Bridge Device
When a first device connected to a first local bus requests to write data in a second device connected to a second local bus, the bridge device acquires the use of the second local bus and request to write data in the target device in place of the master device. When the master device acquires the use of the first local bus, the data that is to be written in the target data is sequentially output from the master device. The bridge device stores the data output from the master device in its internal buffer. When acquiring the use of the second local bus, the bridge device sequentially outputs the stored data to the target device. Such data write via a bridge device is called "posted write".
As described above, both in delayed read and posted write, the data output from one of the devices is temporarily stored in the buffer in the bridge device. Accordingly, when the capacity of the buffer is relatively large, the period of time taken to fill the buffer with data is relatively long. As a result, the probability that the secondly use of a local bus will be acquired before the buffer is full is relatively high, meaning that delayed reads or posted writes may be performed smoothly.
When the buffer is filled before the second use of a local bus is acquired, the bridge device has to stop the data transfer, and the master device has to give up the first use of a local bus. Under the circumstances, the delayed read or the posted write need to be restarted from scratch. Should the bridge device repeatedly have to restart data transfers from scratch, a large number of devices will have to wait to acquire the use of local buses. As a result, the local buses will be always used highly inefficiently.
Though a larger capacity for the buffer may appear to improve the efficiency with which the local buses are used, increases in this capacity are problematic. This is because the buffer in a bridge device must be an expensive BI-CMOS-type to simultaneously input and output data. The cost of such memory places a restriction on buffer capacity, so that the capacity of the buffer is usually small.
It is normally possible for a device to transfer up to 64 double words of data in one burst data transfer. More, one double word represents 32 bits, and it is possible for a PCI bus with 32 bit width to transfer one double word of data in one clock cycle when overheads, such as for address transfer, are ignored. A bridge device includes a buffer with a capacity much smaller than 64 double words. As one example, the capacity of the buffer for delayed read in a 21152-type bridge device manufactured by DIGITAL EQUIPMENT CORPORATION is 18 double words. With such a buffer, a device that can transfer 64 double words of data in one burst data transfer has to acquire the use of a label bus four times and perform four burst data transfers to read 64 double words of data.
The capacity of the buffer for the posted write is no more than 22 double words of data including an address. Under the circumstances , a device that can transfer 64 double words of data in one burst data transfer has to acquire the use of a local bus three times and perform three burst data transfers to output 64 double words or data.